Senior Analog Layout Engineer - Malaysian Only

• Layout Design Ownership

• Lead the physical layout of complex analog/mixed-signal blocks (e.g., PLLs, ADCs, DACs, power management ICs)
• Perform top-level floor planning and hierarchical layout integration
• Creating and optimizing custom analog layouts using industry-standard EDA tools, focusing on performance, area, and power.
• Advanced Layout Techniques

• Apply matching, shielding, isolation, and parasitic minimization strategies
• Optimize for performance, area, and manufacturability
• Verification & Signoff

• Run and resolve issues from DRC (Design Rule Check), LVS (Layout vs. Schematic), and ERC (Electrical Rule Check)
• Perform parasitic extraction and support post-layout simulations
• Collaboration

• Work closely with circuit designers, verification engineers, and process engineers
• Interpret circuit schematics and translate them into optimized physical layouts
• Mentorship & Leadership

• Guide and review the work of junior layout engineers
• Share best practices and contribute to layout methodology improvements
• Tool Proficiency

• Use industry-standard EDA tools like Cadence Virtuoso, Calibre, and Mentor Graphics
• Scripting knowledge (e.g., SKILL, Python, TCL) is often expected for automation

• Bachelor’s or Master’s in Electrical Engineering, Microelectronics, or related field
• 7+ years of experience in analog/mixed-signal IC layout
• Strong understanding of CMOS and FinFET process technologies
• Proven track record of successful tape-outs

EPS Consultants