Senior Layout Engineer (SerDes)
Advanced Micro Devices
- Pulau Pinang
- Permanent
- Full-time
- Layout design of high speed and high performance SerDes analog mixed signal circuit in accordance to project requirements and specifications.
- Block level physical implementation which includes floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layout.
- Participate in post-layout circuit performance analysis
- Participate in block/IP/chip level integration activities
- Estimate realistic schedule, track and report clear progress and status
- Strong participation in defining layout methodology and flow
- Driving layout productivity improvement initiatives (i.e: pcell development and automation)
- Other responsibilities which include supervision of layout resources (onsite and offsite), assessing and correcting layout quality issues, and providing feedback to design teams.
- 4 year of layout design experience in lower process nodes (7nm or below)
- Good understanding of analog and mixed signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heating
- Good understanding of high speed critical signal routing and shielding
- Strong in physical design verifications (LVS/DRC/ERC/ANT/ESD/etc)
- Familiarity with circuit design concepts/flows and IC manufacturing processes
- Experience in layout of high-speed SerDes blocks and PLLs in advanced Fin-FET process is a plus
- Experience with digital on top integration flow or digital SOC flow is a benefit
- Experience with Cadence SKILL and other programming is a benefit (Perl, Pythong, Tcl, etc ...)
- Ability to work closely with the remote & different time zones design teams
- Excellent team player and good communication skills
- Bachelors or Masters degree in computer engineering/Electrical Engineering.