
Senior Logic Design Verification Engineer
- Pulau Pinang
- Permanent
- Full-time
- Possess a Bachelor's, a Master's degree or a Ph.D. in Electronics Engineering, Computer Engineering, or equivalent with relevant experience in IP/SoC design or verification development.
- At least 8 years of relevant working experience in design verification with UVM and System Verilog.
- Familiarize with UVM Verification Components and Bus-functional Models (BFM) and building Testbench from ground up.
- Strong in UVM application eg UVM Virtual Sequencer, Factory and Formal Property will be advantage.
- Communicates well with good influencing skills.
- Strong in analysis, debugging skills, and creative in problem solving.
- Motivated, Self-driven and Independent.
- Working in Assembly language, embedded firmware, real-time operating system RTOS, BIOS, and HW/SW interactions. Working experience with ACPI spec, power management.
- Hardware-Firmware co-validation development and debugging environments.
- Familiar with Linux, industry scripting languages (Python, Perl), and simulation tools.
- Behavioral traits including, but not limited to, strong written and verbal communication skills, tolerance of ambiguity, problem solving, teamwork, attention to detail, commitment to task, quality focus and Knowledge of Agile.