Job Description: 1. DFT design with hierachical flow which including SCAN/MBIST/ijtag/IP test in a large-scale chip. 2. Assist PD engineers in DFT timing closure. 3. Responsible for DFT patterns verification&simulation. 4. Responsible for ATE patterns generation and debugging with TE. Qualifications: 1. Master with 5+ or Bachelor with 8+ years of DFT/ATE work experience; excellent candidates could be exceptions. 2. Familiar with SCAN/ijtag/MBIST circuit structures and principles, with hierarchical DFT experience, and the ability to independently simulate, verify, and debug. 3. Understanding of basic STA knowledge to perform timing analysis on DFT circuits. 4. Great problem analysis and solving skill; proficiency scripting skills( Python, Perl, etc.) to enhance work efficiency through automation. Further expects: 1. Familiarity with Mentor SSN architecture and design process. 2. Experience in post-silicon ATE debugging, familiarity with SiliconInsight tools.