Packaging Integration Engineer
Western Digital
- Batu Kawan, Pulau Pinang
- Permanent
- Full-time
- This position will interface with wafer fab, mainly NAND and ASIC, package & product design, electrical and physical characterization, lab testing, failure analysis, assembly R&D and other process teams.
- In this position, you will be responsible for influencing package and product design by addressing structural reliability issues particularly and advancing the technology of semiconductor packaging generally.
- Fab process and design understanding and background is preferred.
- As a CPI (chip package integration) engineer, you're responsible for chip structure optimization, package evaluation for Fab process change, package recipe baseline development, etc.
- M.S. or above in Material and Science Engineering, Micro-electronics Engineering, Mechanical Engineering, Semiconductor, Chemical, etc.
- Solid knowledge through academic coursework or experience required in mechanical engineering of IC packaging and related areas.
- Good understanding of Fab process, wafer design and D/S, KGD, MT testing.
- Good understanding of general semiconductor packaging processes, materials, technology and trends, such as substrate design and manufacturing, molding, wire-bonding, die attach, flip chip, etc.
- Strong oral and written communication skills, especially in English, etc.
- Demonstrated strong work ethic.
- Ability to work in a team environment and interact with other engineers to define and implement numerical and lab experiments for feasibility and validation of concepts and solutions to support new package technology development.
- Solid background in applied mechanics and computational techniques is required.
- In-depth knowledge of IC packaging is highly desired.
- Skilled in DOE design and statistical analysis tools is preferred.
- Self-motivated, hardworking, teamwork.